Bulk micromachined capacitive type transducers can provide larger mass and larger transduction area compared to surface micromachined devices. However, higher sensitivity or efficient tuning and feedback by electrostatic force is limited due to the difficulty in fabricating high aspect-ratio (HAR) vertical capacitive sensing/actuation gaps. To achieve minimum gap, device height has to be compromised because of limitations and lag with Deep Reactive Ion Etching (DRIE) limitations and lag.
Researchers have developed several fabrication methods for making small capacitive transduction gaps for MEMS devices. Although the width and aspect-ratio of the gaps are impressive, the device height is still limited by the gap height. For effective gaps of several micrometers, the gap height is typically less than 150 μm. High aspect-ratio sub-micrometer gaps are achievable for gap height at a few tens of micrometers, while other sub-micrometer or sub-100 nm gaps are only found in thin (several micrometers) RF resonators that are surface micromachined.
Among these methods, sacrificial material is most frequently chosen to precisely define high aspect ratio gaps at 1-2 μm or sub-micrometer range. Timing in gas or liquid phase release etching is sensitive and limits the proceeding or subsequent process steps. In addition, the processes result in larger total chip area than the active device in order to ensure structural integrity. Other fabrication processes combine two-sided surface micromachining, bulk micromachining and sacrificial oxide patterning. Full wafer thickness is achieved with the 1.5 μm sensing gap and thickness of 70 μm. Silicon dioxide is used as sacrificial layer and the device is released in HF after anisotropic wet etching of the SCS proof-mass in EDP. Another example is the sub-micrometer gap SCS resonators/accelerometers/gyroscopes made by HARPSS or HARPSS-SOI process where sacrificial oxide is also used to define the gap dimensions. The effective thickness is bonded in the range of 30-150 μm with corresponding gap dimensions definable in the range of 0.1-2 μm. Timing in gas or liquid phase release etching limits the maximum thickness achieved for a minimum gap dimension. Although the device thickness may be increased by back-side processing of the substrate silicon in silicon on insulator wafers, effective sensing/actuation areas are limited to few tens of micrometers because of the device layer thickness and back-filling limitations.
Work has also been done toward the possibility of enhancing the etching properties of photo-assisted electrochemical etching in hydrofluoric acid to create HAR gaps and to replace deep reactive ion etching. Sub-200 nm gaps with ultra HAR of 125:1 have been demonstrated but the height is limited to less than 25 um. Most literature to date only tested uniformly patterned bars, circles or rectangles. Factors including composition of electrolyte, applied bias and photo-intensity of the light source combined affect the etching profile, repeatability and reproducibility.
These existing methods are complicated and not applicable to or optimal for 3-D, small-footprint, thick devices. Wet processing also limits the process window for integrating with other parts of MEMS structure and potential integration with CMOS circuits. Therefore, it is desirable to develop transducers and other types of microstructures having small footprints with high aspect ratios.
This section provides background information related to the present disclosure which is not necessarily prior art.